ispLEVER Release Notes Version 3.1 Service Pack 1 Technical Support Line: 1-800-LATTICE or (408) 826-6002 Web Update: To view the most current version of this document, go to www.latticesemi.com. LEVER-RN 3.1_sp01 Rev. 1 (Supercedes LEVER-RN 3.1_sp01) Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written consent from Lattice Semiconductor Corporation. The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation. Information in this document is subject to change without notice. The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified. Lawful users of this product are hereby licensed only to read the programs on the disks, cassettes, or tapes from their medium into the memory of a computer solely for the purpose of executing them. Unauthorized copying, duplicating, selling, or otherwise distributing this product is a violation of the law. Trademarks Copyright (c) 2003 Lattice Semiconductor Corporation. Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, Beyond Performance, E2CMOS, FIRST-TIME-FIT, GAL, Generic Array Logic, In-System Programmable, In-System Programmability, ISP, ispATE, ispDesignEXPERT, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXVA, ispJTAG, ispLEVER, ispLSI, ispMACH, ispPAC, ispSOC, ispSVF, ispTURBO, ispVIRTUAL MACHINE, ispVM, LINE2AR, MACH, MMI (logo), ORCA, PAC, PAC-Designer, PAL, PALCE, Performance Analyst, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, UltraMOS, V Vantis (design), Vantis, Vantis (design), Variable-GrainBlock, and Variable-Length-Interconnect are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP is a service mark of Lattice Semiconductor Corporation. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 January 2004 ii ispLEVER 3.1 Service Pack 1 Release Notes Limited Warranty Lattice Semiconductor Corporation warrants the original purchaser that the Lattice Semiconductor software shall be free from defects in material and workmanship for a period of ninety days from the date of purchase. If a defect covered by this limited warranty occurs during this 90-day warranty period, Lattice Semiconductor will repair or replace the component part at its option free of charge. This limited warranty does not apply if the defects have been caused by negligence, accident, unreasonable or unintended use, modification, or any causes not related to defective materials or workmanship. To receive service during the 90-day warranty period, contact Lattice Semiconductor Corporation at: Phone: 1-800-LATTICE or (408) 826-6002 E-mail: techsupport@latticesemi.com If the Lattice Semiconductor support personnel are unable to solve your problem over the phone, we will provide you with instructions on returning your defective software to us. The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser. Limitations on Warranty Any applicable implied warranties, including warranties of merchantability and fitness for a particular purpose, are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein. In no event shall Lattice Semiconductor Corporation be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties. Purchaser's sole remedy for any cause whatsoever, regardless of the form of action, shall be limited to the price paid to Lattice Semiconductor for the Lattice Semiconductor software. The provisions of this limited warranty are valid in the United States only. Some states do not allow limitations on how long an implied warranty lasts, or exclusion of consequential or incidental damages, so the above limitation or exclusion may not apply to you. This warranty provides you with specific legal rights. You may have other rights which vary from state to state. ispLEVER 3.1 Service Pack 1 Release Notes iii Contents ispLEVER 3.1 Service Pack 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 UNIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Downloading and Installing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ispUPDATE Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Installation Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 New Production Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Preliminary Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Timing Model Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Improved Windows 2000 Performance for ORCA FPGA and FPSC Devices . . . . . 3 ispXPGA and ispGDX2 CDR Macro Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Verilog Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Verilog Parameter Declaration and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VHDL Architecture and Attribute Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VHDL Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to ispGDX2 and ispXPGA Part Numbers and Bitstream/JEDEC Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Part Number Changes for ispGDX2 and ispXPGA . . . . . . . . . . . . . . . . . . . . . .11 Bitstream/JEDEC Incompatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 ORCA2, ORCA3, ORCA4, and All FPSC Bitstream Direct Programming . . . . . . 12 Documentation Installed as Separate Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Known Issues and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Constraint Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Floorplanner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 ispLSI Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Lattice Logic Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Module/IP Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Online Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ORCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Preference Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 iv ispLEVER 3.1 Service Pack 1 Release Notess Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ispLEVER 3.1 Service Pack 1 Release Notes v ispLEVER 3.1 Service Pack 1 System Requirements System memory requirements for large ispXPGA and ORCA FPGA designs: PC 768 MB RAM minimum 1 GB RAM recommended If using Microsoft Windows 2000, Windows 2000 Service Pack 3 or later is recommended. UNIX 768 MB RAM minimum 1 GB RAM recommended For Solaris 2.8, patch level 13 or higher is required. To find your system's patch level, type: uname -a The machine will return a message similar to following example: SunOS mymachinename 5.8 Generic_108528-15 sun4u sparc SUNW,Sun-Blade-100 In this example, the workstation has patch level 15. ispLEVER 3.1 Service Pack 1 Release Notes 1 Downloading and Installing Instructions To download and install this Service Pack, you can use the ispUPDATE program, which is part of the ispLEVER 3.1 installation. See the ispLEVERTM 3.1 Help for detailed instructions. ispUPDATE Help To open Help and find the "Updating ispLEVER from the Web" topic: 1. From the Project Navigator, choose Help > Process Flow Help. 2. Select any one of the Flows listed. 3. On the Help toolbar, click Help Topics to show the navigation pane on the left. 4. Click to expand the Introduction book, and then choose Updating ispLEVER from the Web. 5. Follow the instructions for starting the ispUPDATE program and using the Update feature. NOTE There may be a pause of several minutes between the download of the service pack and the automatic installation of the service pack. This is normal. Do not click the Start button again. Installation Troubleshooting If you encounter problems installing the Service Pack, do the following: 1. Make sure that no other applications are running. Other applications use essential memory, swap space, and temp space that are also needed by the installer. 2. Remove all the contents of the TEMP directory. Normally, the TEMP directory is set to the C: drive. To verify its location, type SET TEMP in a DOS window and press ENTER. 3. Make sure that your boot drive contains at least twice the byte size of the service pack file. 4. Install using the Run command from the Start menu. This will avoid starting the setup twice inadvertently. If problems persist, use the Control Panel system options to increase the virtual memory and free up disk space on the target drive as well as on the TEMP drive. 2 ispLEVER 3.1 Service Pack 1 Release Notes Enhancements The ispLEVER 3.1 Service Pack 1 includes the following enhancements, which are applicable to both PC and UNIX operating systems, except where noted: New Production Device Support Support is added for the following devices: LC5768MX Preliminary Support This release updates preliminary support for the following device: ispMACH4000Z: LC4256Z Silicon timing delay models for devices with Preliminary Support are based on estimated data, and subject to change. Timing Model Changes Timing models for the following families have been updated in this release: ispXPLD 5000MX This may result in performance changes for designs targeting these families. Check the latest device datasheets at www.latticesemi.com for details. Improved Windows 2000 Performance for ORCA FPGA and FPSC Devices Run times for ORCA FPGA and FPSC devices have been improved for computers using the Windows 2000 operating system. ispLEVER 3.1 Service Pack 1 Release Notes 3 ispXPGA and ispGDX2 CDR Macro Changes For all ispXPGA and ispGDX2 devices, the CDRLOCK, LOSS, and EXLOSS flags have been removed from the following sysHSI macros: CDRX_SS_4 CDRX_SS_6 CDRX_SS_8 CDRX_10B12B CDRX_8B10B If macros containing these flags are used the software will generate an error. Following are examples of the new macros: Verilog Declaration CDRX_SS Declaration (ispGDX2 and ispXPGA) NOTE This example shows a 4-bit data width, but can be altered for 6 and 8 accordingly. module CDRX_SS_4(SIN, SS_CLKIN, CAL, RXD0, RXD1, RXD2, RXD3, RECCLK, CSLOCK, SYDT); parameter IN_FREQ = "125.0000"; input SIN, SS_CLKIN, CAL; output RXD0, RXD1, RXD2, RXD3; output RECCLK, CSLOCK, SYDT; endmodule 4 ispLEVER 3.1 Service Pack 1 Release Notes CDRX_10B12B Declaration (ispGDX2 and ispXPGA) module CDRX_10B12B(SIN, REFCLK, CDRRST, RXD0, RXD1, RXD2, RXD3, RXD4, RXD5, RXD6, RXD7, RXD8, RXD9, RECCLK, CSLOCK, SYDT); parameter IN_FREQ = "60.0000"; input SIN, REFCLK, CDRRST; output RXD0, RXD1, RXD2, RXD3, RXD4, RXD5, RXD6, RXD7, RXD8, RXD9; output RECCLK, CSLOCK, SYDT; endmodule CDRX_8B10B Declaration (ispGDX2 and ispXPGA) module CDRX_8B10B(SIN, REFCLK, CDRRST, RXD0, RXD1, RXD2, RXD3, RXD4, RXD5, RXD6, RXD7, RXD8, RXD9, RECCLK, CSLOCK, SYDT); parameter IN_FREQ = "70.0000"; input SIN, REFCLK, CDRRST; output RXD0, RXD1, RXD2, RXD3, RXD4, RXD5, RXD6, RXD7, RXD8, RXD9; output RECCLK, CSLOCK, SYDT; endmodule ispLEVER 3.1 Service Pack 1 Release Notes 5 Verilog Parameter Declaration and Instantiation CDRX_SS Parameter Declaration and Instantiation (ispGDX2 and ispXPGA) defparam I1.IN_FREQ = "100.0000"; CDRX_SS_4 I1 (.SIN(SIN),.SS_CLKIN(SS_CLKIN),.CAL(CAL),.RXD0(RXD0),.RXD1(RXD1 ),.RXD2(RXD2), .RXD3(RXD3),.RECCLK(RECCLK),.CSLOCK(CSLOCK),.SYDT(SYDT)); CDRX_10B12B Parameter Declaration and Instantiation (ispXPGA Only) defparam I1.IN_FREQ = "70.0000"; CDRX_10B12B I1(.SIN(SIN),.REFCLK(REFCLK),.CDRRST(CDRRST), .RXD0(RXD0),.RXD1(RXD1),.RXD2(RXD2),.RXD3(RXD3),.RXD4(RXD4), .RXD5(RXD5),.RXD6(RXD6),.RXD7(RXD7),.RXD8(RXD8),.RXD9(RXD9), .RECCLK(RECCLK),.CSLOCK(CSLOCK),.SYDT(SYDT)); CDRX_8B10B Parameter Declaration and Instantiation (ispXPGA Only) defparam I1.IN_FREQ = "70.0000"; CDRX_8B10B I1 (.SIN(SIN),.REFCLK(REFCLK),.CDRRST(CDRRST), .RXD0(RXD0),.RXD1(RXD1),.RXD2(RXD2),.RXD3(RXD3),.RXD4(RXD4), .RXD5(RXD5),.RXD6(RXD6),.RXD7(RXD7),.RXD8(RXD8),.RXD9(RXD9), .RECCLK(RECCLK),.CSLOCK(CSLOCK),.SYDT(SYDT)); NOTE CDRRST needs to be inverted for ispGDX2, as shown in the following examples. CDRX_10B12B Parameter Declaration and Instantiation (ispGDX2 Only) defparam I1.IN_FREQ = "60.0000"; CDRX_10B12B I1(.SIN(SIN),.REFCLK(REFCLK),.CDRRST(!CDRRST), .RXD0(RXD0),.RXD1(RXD1),.RXD2(RXD2),.RXD3(RXD3),.RXD4(RXD4), .RXD5(RXD5),.RXD6(RXD6),.RXD7(RXD7),.RXD8(RXD8),.RXD9(RXD9), .RECCLK(RECCLK),.CSLOCK(CSLOCK),.SYDT(SYDT)); 6 ispLEVER 3.1 Service Pack 1 Release Notes CDRX_8B10B Parameter Declaration and Instantiation (ispGDX2 Only) defparam I1.IN_FREQ = "70.0000"; CDRX_8B10B I1 (.SIN(SIN),.REFCLK(REFCLK),.CDRRST(!CDRRST), .RXD0(RXD0),.RXD1(RXD1),.RXD2(RXD2),.RXD3(RXD3),.RXD4(RXD4), .RXD5(RXD5),.RXD6(RXD6),.RXD7(RXD7),.RXD8(RXD8),.RXD9(RXD9), .RECCLK(RECCLK),.CSLOCK(CSLOCK),.SYDT(SYDT)); VHDL Architecture and Attribute Declarations NOTE The following example shows a 4-bit data width, but can be altered for 6 and 8 accordingly. CDRX_SS Architecture and Attribute Declaration (ispGDX2 and ispXPGA) architecture behave of CDRX_SS_4 is component CDRX_SS_4 generic(IN_FREQ : string); port(SIN: in std_logic; SS_CLKIN : in std_logic; CAL: in std_logic; RXD0: out std_logic; RXD1: out std_logic; RXD2: out std_logic; RXD3: out std_logic; RECCLK: out std_logic; CSLOCK: out std_logic); end component; ispLEVER 3.1 Service Pack 1 Release Notes 7 CDRX_10B12B Architecture and Attribute Declaration (ispGDX2 and ispXPGA) architecture behave of CDRX_10B12B is component CDRX_10B12B generic(IN_FREQ : string); port(SIN: in std_logic; REFCLK: in std_logic; CDRRST: in std_logic; RXD0: out std_logic; RXD1: out std_logic; RXD2: out std_logic; RXD3: out std_logic; RXD4: out std_logic; RXD5: out std_logic; RXD6: out std_logic; RXD7: out std_logic; RXD8: out std_logic; RXD9: out std_logic; RECCLK: out std_logic; CSLOCK: out std_logic; SYDT: out std_logic); end component; CDRX_8B10B Architecture and Attribute Declaration (ispGDX2 and ispXPGA) architecture behave of CDRX_8B10B is component CDRX_8B10B generic(IN_FREQ : string); port(SIN: in std_logic; REFCLK: in std_logic; CDRRST: in std_logic; RXD0: out std_logic; RXD1: out std_logic; RXD2: out std_logic; RXD3: out std_logic; RXD4: out std_logic; RXD5: out std_logic; RXD6: out std_logic; RXD7: out std_logic; RXD8: out std_logic; RXD9: out std_logic; RECCLK: out std_logic; CSLOCK: out std_logic; SYDT: out std_logic); end component; 8 ispLEVER 3.1 Service Pack 1 Release Notes VHDL Instantiation CDRX_SS Instantiation (ispGDX2 and ispXPGA) begin I1: CDRX_SS_4 generic map( IN_FREQ => "100.0000",) portmap(SIN => SIN, SS_CLKIN => SS_CLKIN, CAL => CAL, RXD0 => RXD0, RXD1 => RXD1, RXD2 => RXD2, RXD3 => RXD3, RECCLK => RECCLK; CSLOCK => CSLOCK, SYDT => SYDT); end behave; CDRX_10B12B Instantiation (ispGDX2 and ispXPGA) begin I1: CDRX_10B12B generic map( IN_FREQ => "60.0000") portmap(SIN => SIN, REFCLK => REFCLK, CDRRST => CDRRST, RXD0 => RXD0, RXD1 => RXD1, RXD2 => RXD2, RXD3 => RXD3, RXD4 => RXD4, RXD5 => RXD5, RXD6 => RXD6, RXD7 => RXD7, RXD8 => RXD8, RXD9 => RXD9, RECCLK => RECCLK, CSLOCK => CSLOCK, SYDT => SYDT); end component; ispLEVER 3.1 Service Pack 1 Release Notes 9 CDRX_8B10B Instantiation (ispGDX2 and ispXPGA) begin I1: CDRX_8B10B generic map( IN_FREQ => "70.0000") portmap(SIN => SIN, REFCLK => REFCLK, CDRRST => CDRRST, RXD0 => RXD0, RXD1 => RXD1, RXD2 => RXD2, RXD3 => RXD3, RXD4 => RXD4, RXD5 => RXD5, RXD6 => RXD6, RXD7 => RXD7, RXD8 => RXD8, RXD9 => RXD9, RECCLK => RECCLK, CSLOCK => CSLOCK, SYDT => SYDT); end component; 10 ispLEVER 3.1 Service Pack 1 Release Notes Changes to ispGDX2 and ispXPGA Part Numbers and Bitstream/JEDEC Algorithms Device selection part numbers for the ispGDX2 and ispXPGA families have been modified to reflect changes in the bitstream/JEDEC algorithms used for these device families. Part Number Changes for ispGDX2 and ispXPGA The original OPN numbers in the ispLEVER 3.0, 3.0 Service Pack 1, and 3.0 Service Pack 2 software for ispGDX and ispXPGA device families have been removed in ispLEVER 3.1 and ispLEVER 3.1 Service Pack 1. The following families are affected by this change: ispGDX2 family: Device selection part numbers now include the suffix "2R." ispXPGA family: Device selection part numbers now include the suffix "ES/2X." Contact your local field sales representative of Lattice Technical Support at techsupport@latticesemi.com if you have questions. NOTE Designs that target affected devices, when imported to ispLEVER 3.1 Service Pack 1 software, default to target the ispLSI5KVE device. These designs should be retargeted to the new part numbers for the ispGDX2 and ispXPGA families accordingly. Bitstream/JEDEC Incompatibility The change affects only designs that utilize the sysHSI function, and only affects the bitstream/JEDEC generated for the affected devices. In that design case, bitstream/JEDEC files generated using any previous version of ispLEVER software will be incompatible with silicon. You will need to force recompile the entire design in ispLEVER 3.1 Service Pack 1 software. ispLEVER 3.1 Service Pack 1 Release Notes 11 ORCA2, ORCA3, ORCA4, and All FPSC Bitstream Direct Programming In the ispLEVER 3.1 software, ORCA2, ORCA3, ORCA4 and all FPSC Bitstream Files (.bit) now contain header file information appended to beginning of the Bitstream File. If you are not using the ispVM software to program the part, and are programming directly with the BIT file, you may receive an error. The error is caused by the addition of the header file information. The problem can be resolved by simply removing the header information from the BIT file. In subsequent releases, there will be an option in the Properties dialog box for the Generate Bitstream process which will allow the user to produce a BIT file with "No Header." Documentation Installed as Separate Module The online Help and User Guides module is optional for the installation of the ispLEVER Starter software. If this module is not downloaded and installed, the following message is displayed when you click a dialog box Help button: The topic does not exist. Contact your application vendor for an updated Help file. (129) Install the online Help and User Guides module from the Lattice web site to eliminate this message. 12 ispLEVER 3.1 Service Pack 1 Release Notes Known Issues and Solutions NOTE All issues pertain to both PC and UNIX, except where noted. Constraint Editor Issue: Routing of memory blocks and arithmetic functions to I/O pins is restrictive. It is very difficult to manually assign pins for these functions so that the assignments will be compatible with the device architecture. Incompatible pin assignments are likely to cause the fitter to fail to partition the design. Workaround: First, let the design run through the software flow without any pin locking. This allows the fitter to choose compatible placement for the functions (you should allow the fitter to run without any pin locking constraints until you absolutely have to lock down the pinout). Second, backannotate the pin assignments (the location assignments of the memory and arithmetic will be automatically written into the constraints file) as you continue to make changes to your design. This gives the fitter a known compatible placement of these functions. Devices Affected: ispXPLD 5000 MX ispLEVER 3.1 Service Pack 1 Release Notes 13 Floorplanner Issue: The pins on the ASIC (non-FPGA core) side of an FPSC device are fixed, but the Floorplanner allows them to be moved via drag & drop. The placer will issue a warning and disregard the invalid assignment. Workaround: None needed. Devices Affected: FPSC Issue: The Floorplanner exits automatically if you invoke a pre-map logical design floorplan or post-map physical design floorplan with Floorplanner already up and running. Workaround: Close the Floorplanner before invoking pre-map logical design floorplan or post-map physical design floorplan. Devices Affected: ORCA FPGA and FPSC Issue: UNIX Only - Some items in Floorplanner may be difficult to view because of problems with color display. Workaround: Adjust colors in Floorplanner using the Color Legend dialog box. Refer to the Floorplanner Online Help for procedures on how to adjust colors in Floorplanner. Also, the Mainwin Control Panel on your UNIX computer may need to be adjusted to correct the colors in Floorplanner. Devices Affected: ORCA FPGA 14 ispLEVER 3.1 Service Pack 1 Release Notes Installation Issue: PC Only - PC Only - After each of the ispLEVER Starter modules are installed, the setup program will configure the system and remove temporary files from the hard drive. This may take up to one minute depending on the speed of the computer and the size of the module installed. During this time, it appears that the setup program has completed with the exception of the Install Shield Icon in the Windows Task Bar. If another ispLEVER module is started before the previous module has actually finished, an error message is generated and the setup program will close. Workaround: Be sure that the Install Shield icon has disappeared before attempting to start the setup program for the next module of ispLEVER Starter software. Devices Affected: Not applicable. ispLSI Macros Issue: PC Only - When an ispLSI Macro with OE port is used for an ispLSI5000VE VHDL/Verilog design, a BLO file is generated. This causes design failure. The following macros are involved: OT11 OT14 OT18 OT21 OT24 OT28 OT31 OT34 OT38 OT41 OT44 OT48 Workaround: Do not use the macro in such a design. Use the behavior description instead. Devices Affected: ispLSI 5000VE ispLEVER 3.1 Service Pack 1 Release Notes 15 Lattice Logic Simulator Issue: When you simulate a design using the Lattice Logic Simulator, the functional simulation process sometimes displays incorrect logic information. Workaround: Adjust the test bench stimulus to transition the data of the flip-flop prior to the clock edge or run the timing simulation. Device Affected: CPLD Module/IP Manager Issue: A FIFO 512x32 memory block, with 28 or less data outputs can be implemented with one MFB. The software currently uses two MFBs to implement the memory block. The data portion of the FIFO is placed in one MFB and the FIFO Flag logic in a second MFB. The portion of the second MFB not used for the FIFO flag logic is available for non-memory logic function placement. Workaround: None. Devices affected: ispXPLD 5000 MX Issue: ORCA module and FPSC CORE dialog boxes have non-functioning links to datasheets. Workaround: Click on Help button for more information on modules and FPSC cores. More information on all modules and cores, including data sheets, brochures, and downloads, can be found on the Lattice Semiconductor Corporation web site at the following URL: http://www.latticesemi.com/products. Devices Affected: ORCA FPGA and FPSC 16 ispLEVER 3.1 Service Pack 1 Release Notes Issue: PC Only - A synchronous FIFO with some parameters (or any other block using a ROM16X1 element) generated for an ORCA4 device with Module/IP Manager can cause an error message when run through the Project Navigator ORCA design flow. The error states that there is a problem converting ROM unit. Workaround: This is a problem with Synplicity 7.3.3. The initval attributes in the Verilog HDL or VHDL source code should be written in the form "OxAEAE." However, Synplicity writes the initval attribute in the form "OxOxAEAE" for ROM16X1 elements for ORCA 4. Edit the HDL source code to remove the extra "Ox" and re-run the design flow in Project Navigator. Later versions of Synplify, such as 7.5.3, should fix this problem. Devices Affected: ORCA4 Issue: If you are using a module generated by the ispLEVER version 3.0 Module/IP Manager, note that ispLEVER 3.1 module/port naming has changed. This is only an issue if you attempt to modify the 3.0-generated module in version 3.1 Module/IP Manager. The place and route tools are backward-compatible. If the module parameters need to be changed there are two options available:. Workaround: Make the changes manually in the source file instantiation. or Re-generate the module using the ispLEVER version 3.1 Module/IP Manager. For a mapping of old to new module/port names, contact Lattice Technical Support. Devices Affected: ispXPGA Issue: The definition for ispXPLD CAM Memory File is incorrect in the online help. The correct definition should read as follows: Memory File Allows you to browse to and open a CAM Initialization File for the module. The file contains initialization data for CAM. Workaround: Not applicable. Devices Affected: ispXPLD ispLEVER 3.1 Service Pack 1 Release Notes 17 Online Help Issue: Clicking the Help button on the ispUPDATE dialog box produces a dialog box that displays the following error message: Cannot find the ../../ispcpld/bin/concepts.hlp file. Do you want to try to find this file yourself? Workaround: Click No in the error message dialog box. Navigate to the../isptools/ispcpld/bin directory, and manually open the flow.hlp file. Click the Help Topics button in the toolbar, expand any of the Flow books, expand the Introduction book, and select the "Updating ispLEVER from the Web" topic. Devices Affected: All Issue: Adobe Acrobat documents (.pdf) may not display artwork correctly if using a version of Adobe Acrobat Reader that is older than version 4.0. Workaround: Install Adobe Acrobat Reader 4.0 or higher to view PDF documents. Devices Affected: All 18 ispLEVER 3.1 Service Pack 1 Release Notes ORCA Issue: Before you perform a JTAG Read and Save operation on an ORCA4 or FPSC device, you must first instantiate the BNDSCAN library element into your design, enable the appropriate bitgen settings, and program the device. Workaround: In the Project Navigator: 1. Using a text editor, instantiate the BNDSCAN library element into your design. 2. In the Processes window, right-click the Generate Bitstream Data process and select Properties. 3. In the Properties dialog box, - Select JTAG After Configuration from the Properties list, and then Select True from values list at the top of the dialog box. - Select Allow Readback from the Properties list, and then select Command from the values list. 4. Click Close. 5. In the Processes window of the Project Navigator, click the Bitstream Data File process. In the ispVM System: 6. Add the ORCA4 or FPSC device, set the chain operation to Program and Verify, and select the Bitstream Data file generated by Project Navigator. 7. Choose Project > Download to program the device. 8. After the device has been programmed, set the chain operation to Read and Save. 9. Choose Project > Download to perform the Read and Save operation. Devices Affected: ORCA FPGA and FPSC ispLEVER 3.1 Service Pack 1 Release Notes 19 Issue: PC Only - There two versions of bitgen in the ispLEVER software: one for CPLD devices located under <install_path>\ispcpld\bin, and one for ORCA devices under <install_path>\ispfpga\bin\NT. The Project Navigator will always use the correct version of bitgen, depending on your project. However, when running ispLEVER programs via command line in ispLEVER Console for ORCA devices, the CPLD bitgen will be selected because the default path points to <install_path>\ispcpld\bin first. UNIX Only - There two versions of bitgen in the ispLEVER software: one for CPLD devices located under <install_path>/ispcpld/bin, and one for ORCA devices under <install_path>/ispfpga/bin/sol. The Project Navigator will always use the correct version of bitgen, depending on your project. However, when running IspLEVER programs via command line in ispLever Console for ORCA devices, the CPLD bitgen will be selected because the default path points to <install_path>/ispcpld/bin first. Workaround: PC Only - To use the ORCA bitgen using command line, you must first manually set <install_ path>\ispfpga\bin\NT in the PATH. UNIX Only - To use the ORCA bitgen, you must first manually set <install_path>/ispfpga/bin/sol in the PATH. Devices Affected: ORCA FPGA Issue: For better compatibility with simulators, all negative setup/hold delay numbers in the Standard Delay Format (.sdf) file are set to 0 by default. This may cause some discrepancies between back annotation and the TRACE (trce) timing analysis result. Workaround: Use the new -neg option to get the negative numbers in the SDF file and back annotation will match the TRACE report. But make sure that the simulator will be able to handle negative numbers in the SDF file. For example, the following command generates Verilog netlist and SDF file without setting the negative setup/hold delays to 0: ldbanno -neg -n verilog design.ncd Devices Affected: 20 ORCA FPGA and FPSC ispLEVER 3.1 Service Pack 1 Release Notes Place and Route Issue: Input registers should be assigned automatically for the M4A devices, but it is possible that no input registers will be assigned. This is due to the fitter requirement that all GLBs have a consistent macrocell to pin ratio, such as 16/8. In some M4A devices, the ratio in one GLB may be different than the ratio in another GLB. Therefore, the input registers will not be assigned properly for this device. Workaround: You can target the M4A3512/256 device and reserve pins so that the pinout of the desired device is meet. You can then program the M4A3-512/160 device, or the M4A3-512/192 device, using the M4A3-512/256 JEDEC file. Contact Lattice Technical Support to obtain a constraint file with the correct pins reserved for the device being used. Devices Affected: ispMACH4A3-512/160 and ispMACH4A3-512/160 PLL Issue: PLL implementation of Schematic/Verilog PLL design is incorrect for ispMACH 5000VG. Though the design compiles correctly, the fitter report shows that one of the internal nodes is automatically forced by the software as an output. Though signals appear in the report correctly, the summary shows that another output is generated: the internal node has become an output and the output is locked to a specific pin. Workaround: None. Devices Affected: ispMACH 5000VG Issue: If the PLL clock output is connected to logic, it should also be connected to a pin. This will not introduce extra pin usage because the PLL clock output can be connected to logic only through the pin feedback.A buffer is not considered logic. If the PLL clock output is connected to a pin through an inverter, an extra clock output connection to a pin is not needed, unless the output of the inverter has a fanout greater than 1. Workaround: None Devices affected: ispXPLD 5000MX ispLEVER 3.1 Service Pack 1 Release Notes 21 Preference Editor Issue: Pin locate attributes defined in the HDL are not visible in the post-map Preference Editor. These preferences are between SCHEMATIC START/SCHEMATIC END statements in the post-mapped preference file (.prf). Place and route will honor pin locates from HDL, and using Preference Editor to set pin locates (including overriding those from HDL) will also be honored. Similarly, frequency attributes defined in the HDL are not visible in the Preference Editor. Workaround: To make HDL preferences visible in the Preference Editor post-map, use Edit Constraints (ASCII) or any text editor to move these preferences to after the SCHEMATIC END statement. They will then be visible in the Preference Editor. Devices Affected: ORCA FPGA Issue: UNIX Only - Some items in Preference Editor may be difficult to view because of problems with color display Workaround: Adjust colors in Preference Editor using the Set Colors dialog box. Refer to the Preference Editor Online Help for procedures on how to adjust colors in Preference Editor. Also, the Mainwin Control Panel on your UNIX computer may need to be adjusted to correct the colors in Preference Editor. Devices Affected: ORCA FPGA Project Navigator Issue: Source files opened, and then saved, in Text Editor could fail to generate database if blank spaces are left in the file name. Workaround: Don't leave blank spaces in file names of source files saved in the Text Editor. Devices Affected: All 22 ispLEVER 3.1 Service Pack 1 Release Notes Issue: Project Navigator does not update the automake.log file shown on the screen with the ORCA Foundry tool's standard output until the process is complete. This means, for example, that a long place and route run will not update the screen output until the job is done and that the status will not be shown while the job is running. Workaround: You can view the standard output message log of the running process in your computer's console window. Devices Affected: ORCA FPGA Issue: When a new project is created in the same directory as an existing project, the revision control for the old project appears in the Revision Control window. Workaround: None. Do not create multiple projects in the same directory when Revision Control is enabled. Devices Affected: ispXPGA, ORCA FPGA Issue: If you to run the ISC-1532 File process in ispLEVER Project Navigator without having the ispVM System software installed on your computer, you will receive an error message. Workaround: Ensure that you have the latest available version of the ispVM System software installed on your computer before running the ISC-1532 File process in Project Navigator. If you are using ispLEVER Starter software, you must download the ispVM software from the www.latticesemi.com website, and install the ispVM software in your <install_path>\ispTOOLS directory Devices Affected: All IEEE 1532 compliant devices. ispLEVER 3.1 Service Pack 1 Release Notes 23 Issue: UNIX Only - Long PATH variables in C-Shell prevent usage of LEVER tools.When running an ispLEVER tool such as Floorplanner, in C-shell (csh) from the ispgui tool, an unusually long PATH variable (e.g. 600-700 characters) will prevent its usage. Specifically, the csh truncates PATH causing missing runtime library and other errors related to this restriction and generates error messages. Workaround: To avoid this error, ensure the path does not exceed the allowable length for your particular version of csh. If you receive a "long path" error message, you must exit ispgui, reduce the path length, and attempt to open your design file using ispgui again. Devices Affected: All Issue: There are two executable files in the ispLEVER software named bitgen.exe that perform the different functions. The path to the files are: <install_path>/ispcpld/bin/bitgen.exe <install_path>/ispfpga/bin/sol/bitgen.exe This could cause problems if you are using the command-line to run the software. Workaround: None Devices Affected: All Issue: UNIX Only - If you use uppercase for a module name in your project (for example, Flicker.abl), the UNIX version of Project Navigator will report an error. Workaround: Avoid the use of uppercase letters for module names when you are using a UNIX version of ispLEVER. Devices Affected: All 24 ispLEVER 3.1 Service Pack 1 Release Notes Issue: UNIX Only - Under Options->Environment, if you select Use Your Favorite Text Editor, the text editor is not found. Workaround: Use the default text editor and deselect Use Your Favorite Text Editor in Options->Environment. Devices Affected: All Issue: UNIX Only - The ispLEVER window bounces to the bottom of other windows when it loads a project or to the top when it finishes loading. It may also become "sticky," following on every virtual window. This seems to be related to fvwm2 on openwin. Workaround: None. Devices Affected: ORCA FPGA Issue: If your design contains a number of I/O pins that are near to the device I/O limit, you may see the following warning during the first iteration of place and route design backannotation: <Warning> W79003: User defined resource reservation has been ignored. This error is output if the placer can't fit the design. If the design is run through a second iteration, the following error messages will be output: <Error> F51078: There are conflicting pad assignment for signals in Constraint File. Pad "<pin_name>" specified in Constraint File for signal "<signal_name>" has conflict with pad reservation. <Error> F54009: User input file error. <Error> F00001: Placement failed. Workaround: Ensure that your design temporary constraint file (design_name.lct) matches your design constraint file (design_name.lco). If the LCT file does not match the LCO file, delete the [Resource Reservation] portion of the LCT file, and re-run place and route. Devices Affected: All ispLEVER 3.1 Service Pack 1 Release Notes 25 Simulation Issue: When a register signal drives a RAM/FIFO/CAM block and at the same time outputs to a pin, it will cause a failure during timing analysis and Standard Delay File (.sdf) file generation. Workaround: The failure can be prevented by preserving the register signal in the design source code. The following examples show a workaround for a VHDL design: Exemplar: Attribute Attribute Attribute Attribute preserve_signal: boolean; preserve_signal of reg_out: signal is true; OPT : string; OPT OF reg_out : SIGNAL IS "KEEP"; Synplicity: Attribute Attribute Attribute Attribute syn_keep: boolean; syn_keep of reg_out : signal is true; OPT : string; OPT OF reg_out: SIGNAL IS "KEEP"; Where signal reg_out is the Q output of the register that drives the memory block. Devices Affected: ispXPLD 5000MX Issue: CDR and FIFO are not supported in the Lattice Logic Simulator. Workaround: Use ModelSim simulator. Devices Affected: ispGDX2 26 ispLEVER 3.1 Service Pack 1 Release Notes Revision History This version of ispLEVER 3.1 Service Pack 1 Release Notes contains updated information that is not contained in the previous version of this document. Changes include: Page 12- Information has been added that describes how the online Help and User Guides module is optional for the installation of the ispLEVER Starter software. Page 14 - A new known issue has been added for the ispLEVER Starter software installation. Page 22- A known issue describes how an error message is generated in Project Navigator if you run the ISC-1532 File process without having first installed the ispVM System software. This known issue now has information for users of ispLEVER Starter software about how to download the ispVM software from the Lattice Semiconductor Corporation website. ispLEVER 3.1 Service Pack 1 Release Notes 27